1. Field of the Invention
The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit for converting a signal level of ECL (Emitter-Coupled Logic) to a signal level of CMOS (Complementary Metal Oxide Semiconductor).
2. Description of the Prior Art
Recently, so-called Bi-CMOS circuits have come into popular in semiconductor circuit fields. The Bi-CMOS circuits have a combined structure of bipolar circuits and CMOS circuits formed together on one single chip. Bipolar circuits such as ECL LSIs typically provide fast circuit speeds, reduced delay per unit load, and have historically been the predominate technology applied in ICs (Integrated Circuits). CMOX circuits provide high noise immunity, high input impedance, and low power consumption, and have rapidly gained acceptance in the industry. Thus the Bi-CMOS circuits may have the features of both the bipolar circuits and the CMOS circuits.
To use CMOS LSIs (Large Scale Integrated circuits) together with ECL LSIs, the input-output signal levels of both LSIs must be matched and in particular, an interface circuit for converting a signal of an ECL level (high level; about--0.7 volts, low level; about--2.5 volts) to a signal level of a CMOS level (high level; power source potential, i.e., about 5.0 volts, low level; ground potential, i.e., around 0 volts) is necessary.
One previsouly known circuit converting the ECL logic level to the CMOS logic level comprises a pair of differentially connected first and second NPN transistors, a current source connected between the common emitter terminals of the first and second NPN transistors and a ground potential source, a first P-channel MOS transistor (referred as PMOS transistor hereafter) and a pair of complementally connected second PMOS transistor and an N-channel MOS transistor (referred as NMOS transistor hereafter). The first NPN transistor has a collector terminal connected directly to a power source with a potential of about 5.0 volts and a base terminal connected to a non-inverse input terminal for receiving non-inversed ECL logic signal. The second NPN transistor has a collector terminal connected to a power source via the source-drain path of the first PMOS transistor and a base terminal connected to an inverse input terminal for receiving inversed ECL logic signal. The second PMOS transistor has a source terminal connected to the power source, a drain terminal connected to an output terminal for outputting a CMOS level signal and a gate terminal connected to a gate terminal of the first PMOS transistor. The NMOS transistor has a source terminal connected to the ground potential source, a drain terminal connected to the output terminal and a gate terminal connected to a gate terminal bias source. The common gate terminals of the first and second PMOS transistors are connected to the collector terminal of the second NPN transistor.
When high and low level ECL Logic signals are applied to the non-inverse and inverse input terminals respectively, the first NPN transistor becomes conductive while the second NPN transistor becomes non-conductive. In this state, the first and second PMOS transistors connected to the second NPN transistor are rendered non-conductive together. The NMOS transistor is however rendered conductive, since its gate terminal is applied a gate terminal bias from the gate terminal bias source. Thus a current flows into the NMOS transistor from a load connected to the output terminal. Therefore the output terminal becomes the ground potential level, i.e., the low CMOS logic level.
When on the other hand low and high level ECL Logic signals are applied to the non-inverse and inverse input terminals respectively (opposite to the above case), the first NPN transistor becomes non-conductive while the second NPN transistor becomes conductive. In this state, the collector terminal of the second NPN transistor becomes a low level near the ground potential. The first and second PMOS transistors are both rendered conductive since their gate terminals are connected to the collector terminal of the second NPN in the low level. In this state, the second PMOS transistor flows a current from the power source to the output terminal, which is larger than the current flowing through the NMOS transistor. This causes the potential of the output terminal to be the potential of the power source, i.e., the high CMOS logic level.
Thus the conventional level conversion circuit converts the level of the ECL logic signal to the level of the CMOS logic signal.
In the circuit, however, the gate terminal bias potential is so set that the NMOS transistor always operates in the non-saturation region. Therefore, the NMOS transistor fails to give its maximum ability for flowing the load current from the output terminal to the ground potential source when the high and low level ECL Logic signals are applied to the non-inverse and inverse input terminals respectively. As a result, the level conversion circuit fails to change the output level on the output terminal to the low CMOS logic level at a rapid speed. Further, the current flowing the second PMOS transistor flows partially into the NMOS transistor when the low and high level ECL Logic signals are applied to the non-inverse and inverse input terminals respectively. This also fails to cause the circuit to change the output level on the output terminal to the high CMOS logic level at a rapid speed. Thus the conventional level conversion circuit had the drawback that it is difficult to perform the level conversion in a rapid circuit speed.
The conventional level conversion circuit has also another drawback that it consumes a relatively large power. That is, the NMOS transistor operates in accompanying with a tolerable amount of impedance when the high and low level ECL Logic signals are applied to the non-inverse and inverse input terminals of the circuit. Because the NMOS transistor is biased to the operation in the non-saturation region. Also the NMOS transistor continues to operate and flows a relatively large amount of current therethrough after when the ECL Logic signals changed to the opposite polarities. Then the NMOS transistor unnecessarily consumes a fairly large amount of power both when the circuit outputs the high and low CMOS logic level outputs.